ALL videos are automatically posted to the UBC Panopto page for CPEN 211 after the end of lecture. To help you find older lectures by topic, links to videos from the 2024 offering of CPEN 211 will be put in the table below 1 to 2 weeks after lecture, along with a brief description and slide numbers.
Lecture videos:
| Date + link to video | Slide Numbers | Topics |
|---|---|---|
| 09-05 | intro; ss1 (1-17) | Course introduction; Digital abstraction, effect of noise on analog and digital systems |
| 09-10 | ss1 (17-56) | buffer, impact of noise on large circuits, voltage ranges, representing information, integers in binary, combinational vs. sequential logic |
| 09-12 | ss1 (57-84) | combinational vs. sequential logic, boolean algebra, axioms, principle of duality, useful boolean properties, normal form |
| 09-13 | ss1 (86-end); ss2 (1-53) | Shannon expansion; From equations to gates, basic logic gates, bubble rule, gates to equations, NFET and PFET transistors, switch logic, CMOS logic gate design |
| 09-17 | ss2 (56-end); ss3 (1-16) | NAND and NOR gates, tristate inverter, standard cell design, series-parallel networks, complex gates; One-hot, decoder, encoder, multiplexer |
| 09-19 | Flipped Lecture #1: KMaps | |
| 09-24 | Flipped Lecture #2: Sequential Logic | |
| 09-26 | ss3 (17-48) | Multiplexer design, logic with muxes, what's inside an FPGA, read-only-memory, large encoder |
| 09-27 | ss3 (48-end); ss6 (1-27) | Large decoders; Why Verilog?, Verilog modules, 9 rules of debugging, expressions, literal numbers |
| 10-01 | ss6 (27-64) | Verilog: busses, `define, conditional operator (?:), the always block, if statements, case statements, begin/end, ambiguous else |
| 10-03 | ss6 (64-98) | Verilog building blocks: decoder, encoder, module instantiation, implicit vs. named association, module parameters, type 1 synthesis rules |
| 10-08 | ss6 (99-end); ss7 (1-2) | type 1 synthesis rules examples, flip-flop verilog preview, combinational logic test benches, initial block, top level module |
| 10-10 | ss7 (1-42) | D flip-flop, non- vs. blocking assignments, simple FSM, gate level sim, 2 case FSM, output delay, hierarchical signal names |
| 10-15 | ss7 (41-74); ss8 (1-12) | FSM test benches, less error prone FSM style, Type 2, 3, 4 synthesis rules; Hexadecimal numbers, arbiter, iterative circuit design |
| 10-17 | ss8 (12-end); ss10 (1-7) | iterative circuit design: arbiter example, priority encoder, magnitude comparator example; Half adder, full adder |
| 10-22 | Flipped lecture #3: ARM ISA (1) | |
| 10-24 | Flipped lecture #4: ARM ISA (2) | |
| 10-29 | ss10 (8-end); ss11 (1-15) | Full from half adders, multi-bit adders, negative integers, 2's complement, overflow; Casex, data path state machines - counter |
| 10-31 | ss11 (14-31); lab 5 | Message from Prof. Steve Wilton (ECE Dept. Head); Symbolic state machines, counter revisited, up/down counter; Lab 5 into and examples |
| 11-05 | ss11 (32-end); ss12 (1-33) | Timer, read-write memory; Datapath/control partitioning, exponent example |
| 11-07 | ss12 (35-end); ss13 (1-17) | ARM example; Tri-state driver in Verilog; Timing: critical path, propagation delay, setup time, hold time, clock-to-Q delay, slack |
| 11-14 | ss13 (17-end); ss14 (1-50) | hold time violations, timing closure; Performance, instruction processing steps, pipelining, structural and data hazards, forwarding |
| 11-19 | Guest Lecture - Erik Lindholm - Death and Life in Silicon Valley: A 35 year career at Silicon Graphics and NVIDIA |
(*) = pre-recorded
Other important videos for CPEN 211:
Lecture videos from 2019 (includes content on recursion, I/O and interrupts, caches, virtual memory and parallel processing that was removed in 2021)
Lecture videos from 2018
Lecture videos from 2016
Quartus/ModelSim Installation Video
Submitting your lab from a laptop or home (using handin when not in MCLD112)
Lab 3-8 Debugging Video
Lab 5 Demonstration of using DE1-SoC with lab5_top.v
Lab 7 Stage 3 Demo using DE1-SoC