CPEN 211 Lecture Videos (2019)

ALL videos are automatically posted to the UBC Mediasite page for CPEN 211 about 15 minutes after the end of lecture. To help you find older lectures by topic, links to videos from the 2019 offering of CPEN 211 will be put in the table below 1 to 2 weeks after lecture, along with a brief description and slide numbers. Slide set numbers are listed as "ssN". In the table below, slide numbers (pNN-MM) refer to the final version of slides (posted after lecture). Again, please note: The instructor (manually) updates the table below only once every other week, so please use the above link if you are looking for a recent lecture not shown below.

Lecture videos:

Date + link
to video Slide Numbers Topics

09-04 intro p1-end; ss1 1-7 Course introduction; What is Verilog? (not recorded due to setup error by UBC IT; refer to slides)

09-05 ss1 7-38 Module syntax; effect of noise on circuits

09-10 ss1 38-93 effect of noise on circuits; representing information; unsigned integers; combinational vs. sequential logic; boolean algebra

09-12 s1 93-end; ss2 1-24 boolean algebra; equations to gates; NAND and NOR gates; Boolean expressions in Verilog

09-17 Flipped Lecture #1: KMaps

09-18 ss2 24-63 Busses in Verilog; Module instantiation; One hot; iterative logic design example: Arbiter

09-19 ss2 61-112 module parameters; bit-slice notation; test benches; Testbench and debugging strategies; top level module; always block; SYNTHESIS RULES (Type 1)

09-24 Flipped Lecture #2: Sequential Logic"

09-26 ss2 111-end; ss5 1-47 begin/end, ambiguous else; finite state machines (FSMs) in Verilog; test benches for FSMs; Multiplexers (1)

10-01 ss5 45-end; ss6 1-15 Less error prone FSM style, Multiplexers (2), Non-blocking assignments, SYNTHESIS RULES (Type 2); Decoder, Encoder, Multiplexers (3)

10-03 ss6 15-28; Lab 5 intro Multiplexers (4): one-hot versus binary select, FPGA internals; Lab 5 introduction

10-08 ss6 29-84 Factoring Muxes, Encoders and Decoders, Priority Encoder, Magnitude Comparator, Read-Only-Memory (ROM), Hexadecimal

10-10 ss6 85-end; ss7 1-31 Adders, Multi-bit Adder, 2"s complement, Subtractor, Overflow; Casex, Datapath State Machines (Counter, Up-down counter)

10-15 ss7 32-end Datapath State Machines (Timer); Datapath/Control partitioning; Read-Write Memory (RAM); 2018 recording

10-17 Lab 6 intro; ss8 p1-66 Lab 6 intro; CMOS Gates: NFET, PFET, NOT, NAND, NOR, AND-gates, Tri-state inverter, Standard Cell Design

10-22 Flipped lecture #3: ARM ISA (1)

10-24 Flipped lecture #4: ARM ISA (2)

10-29 ss8 p67-end; ss9 p1-35 Midterm; Complex Gates; Function calls in ARM: arguments, BL instruction, return value and control, acquiring storage

10-31 ss9 p37-100 Function calls in ARM (continued): Stack spilling/filling, ARM Calling Conventions, >4 arguments, Recursion, fact() example

11-05 ss9 p101-end; ss10 p1-20 Function calls in ARM (continued): fact() example, local variables, ASCII, pointers and structs, optimization; I/O, polling

11-07 ss10 p20-70 Interrupts, Interrupt Service Routines, Interrupts on ARM

11-12 ss10 p70-end; ss11 p1-20 Interrupts on ARM, Pre-emptive Mulitasking; Fixed-point, Error/Resolution/Accuracy, Floating-point

11-14 ss11 p20-end; ss12 1-24 ss11 p20-end; ss12 1-24 | Floating-point (on ARM); Performance, Processor Performance Equation, Pipelining (NOT recorded due to IT error, see 2018 11-15, 11-20 videos)

11-19 ss12 p25-end instruction pipelining, structural hazards, stalling, data hazards, forwarding, pipeline control, control hazards, pipeline timing diagrams

11-21 ss13 p1-53 Memory types (disk, tape, SRAM, DRAM, flash), Caches: temporal & spatial locality, finding data: tags & block offset, LRU, index, set assoc.

11-26 ss13 p53-85 direct mapped caches, set associative caches, write policies; virtual memory, page numbers, page tables

11-28 ss13 p85-end; ss14 p1-end Translation Lookaside Buffers (TLBs), TLB & caches; Flynn's taxonomy, pthreads, synchronization, Amdahl's Law, consistency and coherence

12-03

Date + link to video	Slide Numbers	Topics
09-04	intro p1-end; ss1 1-7	Course introduction; What is Verilog? (not recorded due to setup error by UBC IT; refer to slides)
09-05	ss1 7-38	Module syntax; effect of noise on circuits
09-10	ss1 38-93	effect of noise on circuits; representing information; unsigned integers; combinational vs. sequential logic; boolean algebra
09-12	s1 93-end; ss2 1-24	boolean algebra; equations to gates; NAND and NOR gates; Boolean expressions in Verilog
09-17		Flipped Lecture #1: KMaps
09-18	ss2 24-63	Busses in Verilog; Module instantiation; One hot; iterative logic design example: Arbiter
09-19	ss2 61-112	module parameters; bit-slice notation; test benches; Testbench and debugging strategies; top level module; always block; SYNTHESIS RULES (Type 1)
09-24		Flipped Lecture #2: Sequential Logic"
09-26	ss2 111-end; ss5 1-47	begin/end, ambiguous else; finite state machines (FSMs) in Verilog; test benches for FSMs; Multiplexers (1)
10-01	ss5 45-end; ss6 1-15	Less error prone FSM style, Multiplexers (2), Non-blocking assignments, SYNTHESIS RULES (Type 2); Decoder, Encoder, Multiplexers (3)
10-03	ss6 15-28; Lab 5 intro	Multiplexers (4): one-hot versus binary select, FPGA internals; Lab 5 introduction
10-08	ss6 29-84	Factoring Muxes, Encoders and Decoders, Priority Encoder, Magnitude Comparator, Read-Only-Memory (ROM), Hexadecimal
10-10	ss6 85-end; ss7 1-31	Adders, Multi-bit Adder, 2"s complement, Subtractor, Overflow; Casex, Datapath State Machines (Counter, Up-down counter)
10-15	ss7 32-end	Datapath State Machines (Timer); Datapath/Control partitioning; Read-Write Memory (RAM); 2018 recording
10-17	Lab 6 intro; ss8 p1-66	Lab 6 intro; CMOS Gates: NFET, PFET, NOT, NAND, NOR, AND-gates, Tri-state inverter, Standard Cell Design
10-22		Flipped lecture #3: ARM ISA (1)
10-24		Flipped lecture #4: ARM ISA (2)
10-29	ss8 p67-end; ss9 p1-35	Midterm; Complex Gates; Function calls in ARM: arguments, BL instruction, return value and control, acquiring storage
10-31	ss9 p37-100	Function calls in ARM (continued): Stack spilling/filling, ARM Calling Conventions, >4 arguments, Recursion, fact() example
11-05	ss9 p101-end; ss10 p1-20	Function calls in ARM (continued): fact() example, local variables, ASCII, pointers and structs, optimization; I/O, polling
11-07	ss10 p20-70	Interrupts, Interrupt Service Routines, Interrupts on ARM
11-12	ss10 p70-end; ss11 p1-20	Interrupts on ARM, Pre-emptive Mulitasking; Fixed-point, Error/Resolution/Accuracy, Floating-point
11-14	ss11 p20-end; ss12 1-24	ss11 p20-end; ss12 1-24 \| Floating-point (on ARM); Performance, Processor Performance Equation, Pipelining (NOT recorded due to IT error, see 2018 11-15, 11-20 videos)
11-19	ss12 p25-end	instruction pipelining, structural hazards, stalling, data hazards, forwarding, pipeline control, control hazards, pipeline timing diagrams
11-21	ss13 p1-53	Memory types (disk, tape, SRAM, DRAM, flash), Caches: temporal & spatial locality, finding data: tags & block offset, LRU, index, set assoc.
11-26	ss13 p53-85	direct mapped caches, set associative caches, write policies; virtual memory, page numbers, page tables
11-28	ss13 p85-end; ss14 p1-end	Translation Lookaside Buffers (TLBs), TLB & caches; Flynn's taxonomy, pthreads, synchronization, Amdahl's Law, consistency and coherence
12-03

(*) = pre-recorded

Other important videos for CPEN 211:
Lecture videos from 2018 (some content may change in 2019)
Lecture videos from 2016
Quartus/ModelSim Installation Video
Submitting your lab from a laptop or home (using handin when not in MCLD112)
Lab 3-8 Debugging Video
Lab 5 Demonstration of using DE1-SoC with lab5_top.v
Lab 7 Stage 3 Demo using DE1-SoC