CPEN 211 Lecture Videos (2018)

If you are looking for a lecture which is not shown below: ALL videos are posted automatically immediately after the end of lecture at this URL (sorted by date, but without lecture topic descriptions).

To help you find older lectures by topic, links to videos from the 2018 offering of CPEN 211 can be found below along with a brief description and slide numbers. Slide set numbers are listed as "ssN". Slide numbers (pNN-MM) refer to the final version of slides (posted after lecture).

Lecture videos:
Date + link
to video
Slide NumbersTopics
09-05 intro p1-end Course introduction
09-06 ss1 p1-51 What is Verilog? Module syntax; effect of noise on circuits; representing information.
09-11 ss1 p52-end; ss2 p1-11 Representing information; unsigned integers; combinational vs. sequential logic; boolean algebra; equations to gates
09-13 ss2 p11-46 NAND and NOR gates; Boolean expressions in Verilog; Busses in Verilog; Module instantiation
09-18 Flipped Lecture #1: KMaps -- video capture failed; please refer to 2017 recording here
09-19 ss2 p46-76 One hot; iterative logic design example: Arbiter; module parameters; bit-slice notation; test benches
09-20 ss2 p77-end; Lab 3 Testbench and debugging strategies; top level module; always block; SYNTHESIS RULES (Type 1)
09-25 Flipped Lecture #2: State Machines
09-27 ss5 1-44 Verilog for Finite-State Machines; Testbenches for FSMs; Better FSM Style (1)
10-02 ss5 44-end; ss6 1-20 Better FSM Style (2), SYNTHESIS RULES (Type 2); Combinational Logic - Decoder, Encoder, Mux
10-04 ss6 20-55, lab5 Mux; Shannon Expansion; FPGA internals; Factoring Muxes, Encoders and Decoders; Lab 5 introduction
10-09 ss6 56-92 Priority Encoder; Magnitude Comparator; Read-Only-Memory (ROM); Hexadecimal; Adders
10-11 ss6 92-end; ss7 1-19 Multi-bit Adder; 2's complement; Subtractor; Overflow; Casex; Datapath State Machines (Counter)
10-16 ss7 19-end Datapath State Machines (Up-down counter, Timer); Datapath/Control partitioning; Read-Write Memory (RAM)
10-18 ss8 1-39; Lab 6 CMOS Logic Gates: NFET, PFET, NOT-gate, NAND-gate; Lab 6 Introduction
10-23 Flipped lecture #3: ARM ISA (1)
10-25 Flipped lecture #4: ARM ISA (2)
10-30 ss8 39-end; ss9 1-20 CMOS Logic Gates: NOR-gate, AND-gate, Tri-state inverterr, Complex Gates; Function calls in ARM
11-1 ss9 20-77 Function calls in ARM (continued), Recursion
11-6 ss9 77-end; ss10 1-17 Recursion, ASCII, pointers and structs, optimization; I/O, polling
11-8 ss10 17-62 Interrupts and Interrupt Service Routines
11-13 ss10 62-end; ss11 1-10 Interrupts on ARM, Pre-emptive Mulitasking; Fixed-point
11-15 ss11 10-end; ss12 1-10 Error/Resolution/Accuracy, Floating-point (on ARM); Performance
11-20 ss12 10-end (pre-recorded 11-16) Processor Performance Equation, Pipelining, Structural/Data/Control Hazards

(*) = pre-recorded

Other important videos for CPEN 211:
Lecture videos from 2017 (some content may change in 2018)
Lecture videos from 2016
Quartus/ModelSim Installation Video
Submitting your lab from a laptop or home (using handin when not in MCLD112)
Lab 3-8 Debugging Video
Lab 5 Demonstration of using DE1-SoC with lab5_top.v
Lab 7 Stage 3 Demo using DE1-SoC